DO-254 Compliance Solutions
DO-254 Compliance Solutions
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Aldec's single or mixed language HDL Simulation Tool Suite provides the capabilities of HDL simulation (source level), post-synthesis (gate level) and post place-and-route simulation (timing level), all being performed in one software environment. HDL code linting, code coverage, profiling, automated documentation and waveform comparison tools are included to enhance verification productivity as well. The simulator uses the designers own testbench to verify the design functionality and also provides coverage metrics to measure how effectively the testbench has exercised the design. Simulation results are stored in waveform format and automatically compared to the results from the different stages of simulation. |
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DO-254 CTS
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Verification
- VHDL Simulation
- Verilog Simulation
- SystemC
- SystemVerilog
- Assertions (PSL, SVA and OVA)
- Acceleration/Emulation
- Code Coverage
- Design Rule Checker (LINT)
Specialty Solutions
- In-Hardware Simulation
- DO-254 Compliance
- MATLAB/Simulink Co-Simulation
- Verification IP
- HDL Regression Manager
- NIOS II Co-Verification
- ARM Co-Verification
- Actel RTAX Prototyping
